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Название: ASIC Design and Synthesis: RTL Design Using Verilog
Автор: Vaibbhav Taraate
Издательство: Springer
Год: 2021
Формат: True PDF
Страниц: 337
Размер: 11 Mb
Язык: English
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution.
Автор: Vaibbhav Taraate
Издательство: Springer
Год: 2021
Формат: True PDF
Страниц: 337
Размер: 11 Mb
Язык: English
This book describes simple to complex ASIC design practical scenarios using Verilog. It builds a story from the basic fundamentals of ASIC designs to advanced RTL design concepts using Verilog. Looking at current trends of miniaturization, the contents provide practical information on the issues in ASIC design and synthesis using Synopsys DC and their solution.