Название: Practical Digital Design: An Introduction to VHDL
Автор: Bruce Reidenbach
Издательство: Purdue University Press
Год: 2022
Страниц: 445
Язык: английский
Формат: pdf (true)
Размер: 21.0 MB

The VHSIC Hardware Description Language (VHDL) is one of the two most popular languages used to design digital logic circuits. This book provides a comprehensive introduction to the syntax and the most commonly used features of VHDL. It also presents a formal digital design process and the best-case design practices that have been developed over more than twenty-five years of VHDL design experience by the author in military ground and satellite communication systems. Unlike other books on this subject, this real-world professional experience captures not only the what of VHDL, but also the how. Throughout the book, recommended methods for performing digital design are presented along with the common pitfalls and the techniques used to successfully avoid them. Written for students learning VHDL for the first time as well as professional development material for experienced engineers, this book’s contents minimize design time while maximizing the probability of first-time design success.

Target Audience:
This book is intended to be used as an introduction to the VHDL language for electrical engineering and computer engineering students or anyone in the engineering profession who is exploring the use of VHDL as a digital design vehicle. There is one assumption that is made about the reader: that he or she has prior experience, either academically or professionally, in software programming (using a language such as C) along with experience in Boolean logic design. We will not describe how a do loop executes in C, nor will we discuss the differences in functionality between a Boolean AND and NOR gate—it is assumed that the reader already has this knowledge. Several brief references are made to object oriented programming, but knowledge or experience with an OOP language such as C++ or Java is not a requirement.

The book can be viewed as containing five main sections:

- Section one (chapters 1 through 4) explains the reason why a concurrent language such as VHDL is necessary to model digital electronic circuits, presents the recommended design flow used to create digital circuits, and covers the VHDL design environment, that is, the basic foundational features of the language.

- Section two (chapters 5 through 10) introduces the reader to the concept of design libraries and design units and covers most of the syntax that comprises the actual language. As each syntax element is introduced, examples of typical use and a description of the Boolean logic inferred by each statement is presented.

- Section three (chapters 11 through 13) describes the method by which VHDL models are verified via simulation and discusses how to properly write a test bench to fully test the model. A method of developing a simulation test bench via a test bench template is presented.

- Section four (chapters 14 through 17) introduces the reader to the concept of logic synthesis, with a special emphasis placed on writing VHDL models that can be readily and successfully converted into the actual logic gates that perform the desired function. Code examples for a standard set of common macrolevel digital functions are covered, which can be combined together to create almost any digital logic circuit.

- The final section (chapters 18 through 21) covers several advanced design topics such as state machine design, functional decomposition, and design reuse and provides a detailed narrative using the recommended digital design process for the steps taken to design several real-world logic circuit examples.