Название: Computer Memories 3: Dynamic Random-Access Memory
Автор: Philippe Darche
Издательство: Wiley-ISTE
Год: 2026
Страниц: 224
Язык: английский
Формат: epub (true)
Размер: 14.3 MB

Memory, the second function of a computer, has gradually become more complex in order to meet growing needs in terms of capacity, speed, security and energy efficiency. It takes the form of a component or system, such as a memory subassembly or a mass storage device.

For several decades, there has been a strong trend towards integrating memory directly into the processor under the term embedded memory, of which cache memory is a typical example. Understanding its internal mechanisms and interfacing is essential for mastering the operation of a computer and programming it efficiently.

Computer Memories 3 focuses on asynchronous dynamic random-access memory (DRAM). It examines the memory cell, then the internal organization of a generic memory, before delving into detail regarding the associated component known as DRAM. This book also presents the various access modes and advanced approaches such as embedded memory, 3D cells and capacitance-free cells.

Dynamic random-access memory, or DRAM (dynamic RAM), is currently the most widespread type of external memory in computers, owing to the expansion of the server and microcomputer markets. It is, with read-only memory or ROM, the medium of primary or main memory. It contains the programs currently being executed, those of the operating system and applications, and the data, ROM being reserved for the firmware (FW). Together with the microprocessor, it constitutes one of the most important components of a computer in terms of performance and cost.

It was originally very economical to manufacture because its basic storage principle relied on the parasitic capacitance that exists between the gate and the source of a metal oxide semiconductor (MOS) field-effect transistor, or MOSFET. Since the mid-1970s, the storage element has consisted of a single transistor and a capacitor (1T-1C), as opposed to six transistors (6T) or four transistors and two resistors (4T-R), as in the case of an SRAM cell. As a first approximation, its storage density was therefore four to six times greater. Since 1970, the number of bits per unit area increased by a factor of 4 every three years, causing the price of the stored bit to decrease by approximately the same factor.

This volume immerses us in the first period of DRAM development. The model is essentially asynchronous. The volume consists of five chapters. The first details the operating principle and the different structures of the dynamic storage cell. Chapter 2 presents the other internal subassemblies of a generic dynamic random-access memory. Chapter 3 presents the component and its different access modes, as well as internal refreshing and its packaging. We conclude this volume (Chapters 4 and 5) with the research directions currently being explored, focused on eliminating the storage capacitor.

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